A booster circuit is widely utilized for a circuit that requires a voltage level different from the source voltage, for example, a voltage higher than the source voltage or a negative voltage. An ordinary charging pump-type booster circuit has several boosting stages configured with rectifier elements, such as diodes and capacitors, depending on the required boosted voltage.
FIG. 2 is a circuit diagram showing an example of the configuration of a popular booster circuit. As shown in the figure, said booster circuit is configured with a booster control circuit 10 comprising driving circuits CH1 and CH2, several diodes D1, D2, . . . , D7, and capacitors C1, C2, . . . , C7.
A switching signal SW, as a clock signal having a fixed frequency, is input into the input terminal of the booster control circuit 10. In the booster control circuit 10, the driving circuits CH1 and CH2 hold their respective output terminals T1 and T2 alternately to a high or a low level based on the switching signals SW input.
The diodes D1, D2, . . . , D7 are connected in series between the feed line of a source voltage V.sub.cc and the output terminal T.sub.B of the booster circuit. Terminals of the capacitors C1, C2, . . . , C6 are connected on one end to the midpoints ND1, ND2, . . . , ND6 between the diodes D1, D2, . . . , D7, and the other ends are connected alternately to the output terminals T1 and T2 of the booster circuit 10. The capacitor C7 is connected between the output terminal T.sub.B of the booster circuit and the ground potential GND. Also, m quantity of Zener diodes ZD1, . . . , ZDm are series-connected in parallel with the capacitor C7. Furthermore, the number m of the quantity of Zener diodes is set based on the value of the desired boosted voltage V.sub.B.
When the booster circuit shown in FIG. 2 is at work, the booster circuit 10 outputs the control signal from the output terminals T1 and T2 to be held at the high level and the low level alternately by the driving circuits CH1 and CH2 based on the switching signals SW input. For example, when the output terminal T1 is at the high level and the output terminal T2 is at the low level, potentials at the nodes ND1, ND3, and ND5 are raised due to the capacitive coupling of the capacitors C1, C3, and C5, and as a result, the capacitors C2, C4, and C6 get charged. On the other hand, when the output terminal T1 is at the low level and the output terminal T2 is at the high level, potentials at the nodes ND2, ND4, and ND6 are raised due to the capacitive coupling of the capacitors C2, C4, and C6, and as a result, the capacitors C3, C5, and C7 get charged. Furthermore, at this time, the capacitor C1 connected to the anode side of the diode D1 gets charged by the source voltage V.sub.cc to a voltage lower than the source voltage V.sub.cc by the amount equivalent to the voltage drop in the forward direction of the diode D1.
As described above, the capacitors at the respective boosting stages charge/discharge in turn based on the control signal from the booster circuit 10, whereby the source voltage V.sub.cc and the boosted voltage V.sub.B corresponding to the number of the boosting stages are output from the output terminal of the booster circuit 10. In the case of the booster circuit shown in FIG. 2, while a boosted voltage V.sub.B higher than the source voltage V.sub.cc can be output, a negatively boosted voltage can also be generated by changing the direction of the diodes D1, D2, . . . , D7.
FIG. 3 is a circuit diagram showing an example of the configuration of the driving circuits CH1 and CH2 constituting the booster control circuit 10. As shown in the figure, driving circuits CHi (i=1, 2) are configured with resistance elements R1 and R2, a pnp transistor Q1, and npn transistors Q2, Q3, and Q4. Bases of the transistors Q3 and Q4 are both connected to an input terminal T.sub.in, the collector of the transistor Q3 is connected to the feed line of the source voltage V.sub.cc via the resistance element R1, and its emitter is grounded. Similarly, the collector of the transistor Q4 is connected to the feed line of the source voltage V.sub.cc via the resistance element R2, and its emitter is grounded.
Base of the transistor Q1 is connected to the collector of the transistor Q4, and its emitter is connected to the feed line of the source voltage V.sub.cc. Base of the transistor Q2 is connected to the collector of the transistor Q3, and its emitter is grounded. Furthermore, collectors of the transistors Q1 and Q2 are connected to each other, and the junction point is connected to an output terminal T.sub.out.
Moreover, when the driving circuits CH1 and CH2, shown in FIG. 3, are used to configure the booster circuit 10 shown in FIG. 2, the 2 driving circuits CH1 and CH2 are connected in series, input terminal T.sub.in of the driving circuit CH1 of the former stage is connected to the input terminal for the switching signal SW, and input terminal T.sub.in of the driving circuit CH2 of the latter stage is connected to the output terminal T.sub.out of the driving circuit of the former stage. Furthermore, output terminal of the driving circuit CH1 of the former stage constitutes the output terminal T1 shown in FIG. 2, and output terminal of the driving circuit CH2 of the latter stage constitutes the output terminal T2 shown in FIG. 2.
In the driving circuits CH1 and CH2 shown in FIG. 3, level of the signal from the output terminal T.sub.out is controlled based on the signal input into input terminal T.sub.in. For example, when a high-level signal is input into the input terminal T.sub.in, the transistors Q3 and Q4 are turned on, and the collectors of these transistors are held to the low level. Accordingly, the transistor Q1 is turned on, the transistor Q2 is turned off, and the output terminal T.sub.out is held to the high level. Also, a charge current I.sub.out is output from said output terminal T.sub.out. To the contrary, when the input terminal T.sub.in is held to the low level, the transistors Q3 and Q4 are turned off, and the collectors of these transistors are both held to the high level. Accordingly, the transistor Q1 is turned off, and the transistor Q2 is turned on, so that the output terminal T.sub.out is held to the low level, and a drop current, that is, a discharge current which flows from the output terminal T.sub.out into the ground side via the transistor Q2 is also supplied.
In the booster control circuit configured with the 2-stage driving circuits CH1 and CH2 connected in series in said manner, the output terminals T1 and T2 are held to the high level and the low level alternately based on the switching signals SW input, and the capacitors C1 through C6 of the respective boosting stages shown in FIG. 2 accordingly get charged and discharged repeatedly. As a result, the boosted voltage V.sub.B higher than the source voltage V.sub.cc is output.
Incidentally, in the case of said conventional booster circuit, when an analog integrated circuit having so-called planer structure, in which circuit elements are formed on a plane of a semiconductor substrate, is used, the circuit element, in particular the transistors, may be difficult to form and still attain desired characteristics. For example, when the pnp transistor Q1 shown in FIG. 3 is formed by means of a lateral structure, a parasitic capacitance is added between the base and the substrate due to the nature of said configuration. As a result, because the frequency (f.sub.T transition frequency) at which the current amplification rate .beta. of the transistors becomes 1 decreases, that is, high-frequency characteristics of the transistor deteriorate, when the switching operation is carried out to turn on/off the transistors Q3 and Q4 repeatedly based on the switching signals SW, on/off timing of the transistor Q1 gets delayed, so that the transistors Q1 and Q2 may get turned on at the same time. In such a case, a leak-through current, a cause of an increase in power consumption, flows between the feed line of the source voltage (V.sub.cc) and the ground potential. Furthermore, a large current flows within the circuit due to the occurrence of the leak-through current during the switching operation causing a problem with louder switching noises.
The present invention was made in light of such a problem, and its purpose is to present driving circuits capable of reducing the power consumption and the noise generated during the switching operation as well as a charging pump booster circuit utilizing said [driving circuits].